ASD 2026 Session TUT1: Tutorial Session I

The Directed Self-Assembly (DSA) of block-copolymers (BCPs) has been intensively investigated as a cost-effective and complementary solution to conventional i193nm or EUV lithography for CMOS applications [1-3]. This technology has also showed an interest in beyond CMOS applications such as Single Electron Transistor devices [4], in the fabrication of nano-structures for optoelectronic [5] and photovoltaic devices [6], or in various other technology [7], due to its ability to precisely control nanopatterns over large macroscopic length scale.

This tutorial aims to give an overview of the selective processes required in DSA patterning technique. Indeed, the DSA patterning relies on the precise control of the surface modifications in order to orientate and localize the nanopatterns on the wafer surface. For that purpose, chemoepitaxy and graphoepitaxy approaches, which are the two main ways to perform DSA, will be explained and compared. Based on LETI’s PS-b-PMMA BCP background, surface modifications solutions such as UV exposure, embedded neutral layers, sequential grafting will be then detailed [8-9]. After the self-assembly process, the nanopatterns created by the BCP is usually transferred into the underlayers. For that purpose, one block (ex: PMMA) has to be selectivity removed over the other one (ex: PS) to create the final nanostructures. Different strategies for a selective etching of PMMA over PS will be exposed depending on the BCP morphology and applications (lines, contact or pillars). For example, cyclic PMMA dry etching steps [10], selective ALD [11] or Sequential Infiltration Synthesis (SIS) [12] methods will be discussed. The basics of the DSA patterning will be addressed through a few DSA application examples.

1. Tiron, R. et al, Proc. SPIE 8680, (2013)
2. Jeong, S-J. et al, Materials today 16 (12), (2013)
3. Lee, K. et al. MRS Commun. 15, 1269–1288 (2025)
4. Gharbi, A. et al, Proc. SPIE 10586, (2018)
5. Feougier, R. et al, Proc. SPIE PC12497, (2023)
6. Garozz C. et al, Phys. Status Solidi A 210, No. 8, (2013)
7. Segalman R. A., Materials Science and Engineering, Vol. 48, Issue 6, (2005)
8. Paquet, A. et al, Proc. SPIE 10958, (2019)
9. Pimenta-Barros, P. et al, Proc. SPIE 10584, (2018)
10. Sarrazin, A. et al, J. Vac Sci. Technol B36, 041803 (2018)
11. Gay, G. et al., Nanotechnology, 21, 435301 (2010)
12. Frascaroli, J. et al., ACS applied materials & interfaces 8 (49), (2016)

In advanced logic devices, specific regions of transistors must be highly crystalline, with precise dopant concentration, particularly for junctions and contacts formation. The most effective method to fabricate these high-quality, highly doped regions is epitaxial growth in industrial RP-CVD (Reduced Pressure Chemical Vapor Deposition) reactors.

A critical requirement of this process is localization: epitaxial growth must be precisely confined to areas where crystalline seed layers are exposed, while dielectric regions have to remain free of deposits. Selective Epitaxy Growth (SEG) is a critical technological enabler in advanced Field Effect Transistors.

To achieve high quality selective epitaxy, several approaches have been explored. Historically, straightforward selective epitaxial growth was used to thicken, at relatively high temperatures (e.g. in the 600°C – 750°C range), sources and drains regions with heavily in-situ doped materials such as Si:P or SiGe:B. This was typically done using co-flow processes during which mainstream deposition and etchant gases (such as SiH₂Cl₂, GeH₄, B₂H₆, PH₃ and HCl) were simultaneously fed into the growth chamber. Co-flow processes were up to now well-suited for CMOS mass production as illustrated in Figures 1-3.

Several challenges must nowadays be overcome for advanced technological nodes. First, top transistors have to be fabricated with a drastically reduced thermal budget (e.g. lower than 500°C, ideally close to 400°C) above already existing transistors in monolithic 3D [1] and Complementary FET architectures (CFET) [2]). Second, the demand for aggressive device performance requires ultra-low electrical resistance materials (for sources/drains and contacts). This comes with stringent requirements in terms of morphology, the presence of new materials and aggressive doping levels, all being challenging in terms of growth selectivity control.

However, low-temperature SEG processes present major technical challenges, fueling intense research and innovation in the CVD epitaxy community [3][4][5]].

In this presentation, we will describe some specific features and challenges of advanced SEG processes. We will notably present the innovative solutions implemented to have low temperature SEG, such as the use of new gaseous or liquid precursors, cyclic processes with the alternance of non-selective growth steps and selective etch steps for different process and so on.

[1] D. Bosch at al., 2025, IEDM.

[2] S. Liao et al., 2023, IEDM, pp. 1-4.

[3] E. Rosseel et al., 2024, Meet. Abstr. MA2024-02 2298.

[4] R. Khazaka et al.,2022, Meet. Abstr. MA2022-02 1187.

[5] J. Kanyandekwe et al, 2022, ECS Trans. 109, 121.

Microelectronic devices have advanced from historic planar to complex 3D architectures.Corresponding nanomanufacturing needs selective atomic layer deposition (ALD) and etching (ALE).Vertical pattern transfer relies on unidirectional, anisotropic plasma ALE.Conversely, lateral pattern release without line of sight requires the omnidirectional, isotropic material removal that is provided by thermal ALE or spontaneous etching.

This tutorial will overview selectivity studies, describe materials that have been etched selectively by thermal chemistries, and provide explanations of this selectivity.Strategies to achieve selective thermal dry etching are based on different combinations of thin film materials and reactants, thermodynamic favorability of reactions, stability or volatility of reaction products, as well as reactant pressures and process temperature.

Selectivity has been observed during thermal ALE.Al₂O₃ thermal ALE is a model system defined by sequential fluorination using hydrogen fluoride (HF) and ligand exchange using Al(CH₃)₃.This Al₂O₃ etch mechanism exhibited high selectivity versus ZrO₂ non-etch because ZrF₄ did not ligand exchange with Al(CH₃)₃.Consequently, ZrF₄ provided an excellent etch stop after Al₂O₃ thermal ALE using HF and Al(CH₃)₃.

In contrast, ZrO₂ or HfO₂ thermal ALE using sequential HF and SiCl₄ exposures was selective versus Al₂O₃ non-etch. After fluorination, ZrF₄ or HfF₄ can ligand exchange with SiCl₄, whereas the reaction of AlF₃ with SiCl₄ is thermodynamically unfavorable at 250°C.

Selective TiN thermal ALE has been demonstrated via sequential oxidation using O₃, followed by halogenation to a volatile halide using HF.TiF₄ readily sublimed at 250°C.In contrast, AlF₃, ZrF₄, and HfF₄ are thermally stable even above 300°C.This resulted in Al₂O₃, ZrO₂, and HfO₂ non-etch using O₃ and HF.

Selectivity has also been observed during spontaneous etching.Selective Si spontaneous etching has been demonstrated using consecutive HF exposures that released volatile SiF₄ and H₂ products above 150°C.In contrast, HfF₄ is a thermally stable solid, resulting in HfO₂ non-etch using HF at 275°C.

Selective SiN_x versus SiO₂ spontaneous etching has also been discovered and depends on the presence of polar co-adsorbates during consecutive HF exposures.Anhydrous HF alone formed F^– surface species that selectively etched SiN_x.In contrast, co-dosing NH₃ with HF formed HF₂^– surface species that selectively etched SiO₂.