GaSb is a III-V material with applications as a potential channel material for p-type metal-oxide-semiconductor field effect transistors,¹ optoelectronics in the infrared region,² quantum devices,³ and tunnel field effect transistors.⁴ Prior to application specific processing it is often necessary to remove the GaSb native oxide, which can be quite thick. Such oxides can inhibit subsequent epitaxy and also be a source of traps for devices as a result of defect levels in the energy gap.⁵ The thermal desorption of these oxides in ultra high vacuum has been examined in previous works, but is revisited in this study with dynamic-x-ray photoelectron spectroscopy (dynamic-XPS). Dynamic-XPS allows for the collection of core-level spectra in real time (i.e. data acquisition times are < 1 second). Combined with controlled heating, this allows for detailed chemical temperature-dependent chemical analysis to be carried out with temperature resolutions better than 1 Kelvin. The thermal decomposition of the native GaSb oxides is studied using dynamic-XPS. The expected transfer of oxygen from Sb-O to Ga-O before the eventual desorption of all oxides is observed. However an initial reaction resulting in the reduction of Sb₂O₃ along with the concurrent increase in both Ga₂O₃ and Sb₂O₄ is detected in the temperature range of 450-525 K. Using the relative changes in atomic concentrations of the chemical species observed, the initial reaction pathway is proposed.

A. Nainani, T. Irisawa, Z. Yuan, Y. Sun, T. Krishnamohan, M. Reason, B. R. Bennett, J. B. Boos, M. G. Ancona and Y. Nishi, presented at the Electron Devices Meeting (IEDM), 2010 IEEE International, 2010 (unpublished).

F. Chen, G. Liu, Z. Wei, R. Deng, X. Fang, S. Tian, Y. Zou, M. Li and X. Ma, presented at the Optoelectronics and Microelectronics (ICOM), 2012 International Conference on, 2012 (unpublished).

M. V. Lebedev, E. V. Kunitsyna, W. Calvet, T. Mayer and W. Jaegermann, The Journal of Physical Chemistry C 117, 15996-16004 (2013).

A. W. Dey, B. M. Borg, B. Ganjipour, M. Ek, K. A. Dick, E. Lind, C. Thelander and L.-E. Wernersson, Electron Device Letters, IEEE 34, 211-213 (2013).

A. Ali, H. Madan, A. Kirk, D. Zhao, D. Mourey, M. Hudait, R. Wallace, T. Jackson, B. Bennett and J. Boos, Appl Phys Lett 97, 143502-143502-143503 (2010).

Silicon Germanium (SiGe) is a well-known material for its high mobility and useful applications in strain engineering. Its advantages can be utilized to overcome the challenges when scaling down silicon-based devices. As the interest in introducing new kinds of materials increases, the cleaning and passivation methods also become more significant in order to provide uniform and clean surfaces, which would result in improved electrical properties such as high mobility and low interface trap density (Dit). In this study, combined wet and dry cleaning and passivation of SiGe(100) surface is discussed, using scanning tunneling microscopy (STM), scanning tunneling spectroscopy (STS), and x-ray photoelectron spectroscopy (XPS).

Wet cleaning using 2% hydrofluoric acid (HF) was implemented to strip the native oxide off the SiGe sample but left residual carbon contamination on the surface. Although the oxide layer was removed, additional oxygen adsorbed to the surface during transfer from the HF solution to vacuum chamber. This residual oxygen can be eliminated by keeping the SiGe sample covered in the HF cleaning solution until the sample is introduced to the vacuum chamber or by transferring the sample in an inert environment. Dry in-situ atomic hydrogen cleaning was then implemented to remove the carbon contamination on the surface. A post deposition anneal at 550˚C was used to obtain an atomically clean, flat, and ordered SiGe surface and this was verified using STM. The oxygen and carbon contaminant levels were monitored after each cleaning procedure using a monochromatic XPS. The clean SiGe sample was dosed at room temperature with a saturation dose of H₂O₂(g). STM and XPS measurements indicate that H₂O₂(g) dosing leaves the SiGe surface, which is mostly Ge atoms due to surface segregation, terminated with an ordered monolayer of Ge-OH sites. STS measurements of the Ge-OH sites show the conduction band edge dangling bond states are eliminated due to the passivating Ge–OH bonds, but the Fermi level is pinned near the valence band edge due to the large surface dipole. When the surface is annealed to 310°C, XPS measurements indicate that the –OH species on the surface break bonds with the Ge atom and bond instead to the Si atoms, raising Si atoms towards the surface. XPS also verifies that no oxygen leaves the surface due to the 310°C anneal. Instead, the oxygen remains on the surface in the form on Si-OH or SiO_x species. TMA is subsequently dosed on the surface forming and ordered monolayer of Al-O-Si bonds. STS indicates this unpins the Fermi level, leaving an electrically passive ordered layer which serves as an ideal template for further high-k ALD.

AlGaN/GaN high electron mobility transistors (HEMTs) are of significant interest for high power, high frequency and high temperature devices. However, these are known to experience significant surface related effects, such as large leakage currents and frequency dependent current collapse. Oxidation has been found to have a variety of effects on the atomic and electronic structure of nitride surfaces. Therefore, the oxidation layer and the device performance are closely related. Typically, GaN and AlN are found to form a disordered oxide layer related to high density of states when exposure to with O₂. Miao et al.¹ reported that oxidation of AlN and GaN surface change the density of surface states based on density functional theory (DFT). In their work, a 2 ML crystalline oxide can cause the lowest density of surface states within the band gap. However, experimental evidence of a 2 ML crystalline oxide remains to be established.

In this study, we investigate O₂ plasma- exposed AlGaN surfaces at 300 °C and 550 °C by in situ X-ray photoelectron spectroscopy (XPS), low energy electron diffraction (LEED). The results indicate that a 500°C O₂ remote plasma exposure is able to generate a thin 2 ML ordered oxide on AlGaN surface and the oxide is stable during subsequent ALD processing, in contrast to arsenide surfaces.² The capacitance- voltage (C- V) results indicates that the 2 ML crystalline oxide reduces the D_it and shifts the threshold voltage to positive voltages. The I-V and gate leakage current characteristics for crystalline oxide MOSHEMTs will also be presented. This work is supported by the AFOSR Asian Office of Aerospace Research and Development (AOARD) under Grand No. FA2386- 11- 1- 4077.

References

¹ M.S. Miao, J.R. Weber, and C.G. Van de Walle, J. Appl. Phys. 107, 123713 (2010).

² D. M. Zhernokletov, P. Laukkanen, H. Dong, R. V. Galatage, B. Brennan, M. Yakimov, V. Tokranov, J. Kim, S. Oktyabrsky, and R. M. Wallace, Appl. Phys. Lett., 102, 211601 (2013)

As silicon devices reach the limit of dimensional scaling there is a growing interest in the use of high electron mobility channels, such as In_xGa_1-xAs, in conjunction high dielectric constant (high-k) gate oxides for n-channel Metal-Oxide-Semiconductor Field Effect Transistors (MOSFETs) and tunnel FET (TFETs) based devices. The understanding and control of electrically active defect states at the high-k/In_xGa_1-xAs interface and of charges within the atomic layer deposited (ALD) high-k films will be essential for the successful implementation of high mobility channel materials. The objective of this presentation will be to provide an overview of the current understanding of the density and distribution of electrically active defects at the high-k/InGaAs interface both within the InGaAs energy gap and extending into the InGaAs conduction band. The presentation will focus on InGaAs with a 53% Indium concentration. The electrically active interface state density distribution is determined from fully fabricated InGaAs MOSFET structures based on the full gate capacitance in conjunction with the Maserjian Y-function and Poisson-Schrodinger simulations. Very significant progress has been made in recent years in the passivation and intrinsic elimination of high-k/In_0.53Ga_0.47As interface defects to the point where genuine surface inversion for n and p type InGaAs MOS structures can be achieved and this research will be reviewed. The characteristic signatures of capacitance and conductance for an InGaAs MOS structure in inversion will also be discussed.

Electrically active defects with energies aligned with the InGaAs conduction band are significant for surface inversion mode MOSFETs and can result in a partitioning of charge between free carriers and trapped charge for devices biased above the threshold voltage. The presence of such defect also complicates the extraction of free charge and carrier mobility from device analysis. In this presentation we will also review a new approach where the technique of inversion charge pumping (initially developed for silicon MOSFETs) is applied to InGaAs MOSFETs to determine the free carrier concentration. Results will also be presented which indicate that the duty cycle of the inversion charge pumping technique can be used to discriminate between fast interface states and traps within the oxide for InGaAs MOSFETs biased beyond the threshold voltage.

Previously, it was reported that by adding the third element into the high-k film, the bulk and interface material and electrical properties can be improved [1]. For example, the Zr-doped HfO₂ film (ZrHfO) shows the higher crystallization temperature, a lower interface state density, and a larger effective k value than those of the un-doped HfO₂ film [1,2]. Furthermore, nanocrystals have been embedded into this kind of high-k film for the nonvolatile memory (NVM) application to replace the conventional floating-gate flash memory due to the improved device characteristics and reliability [3]. The nanocrystalline cadmium selenide (nc-CdSe) embedded ZrHfO MOS capacitor has shown excellent charge trapping and retention capabilities [4]. However, most studies on the nanocrystals embedded high-k memory devices are done at the room temperature. Since the temperature in the high density integrated circuit can be much higher than room temperature, it is imperative to study the reliability at a raised temperature [5]. In this paper, the temperature effects on memory functions were investigated on the nc-CdSe embedded sample in the range of 2 0^oC to 120^oC. Compared with the fresh C-V curve, the flat band voltage (V_FB) of C-V curve shifts to the negative or positive gate voltage (V_g) direction after being stressed at -6 V or +6 V for 10 s, respectively. With the increase of the temperature, the magnitude of the V_FB shift increases at -6 V stress but decreases at +6 V stress. With the increase of the temperature, the hole-trapping is enhanced due to the increase of injection and retention of holes to the trapping sites. However, at the high temperature, electrons are possibly transferred through the whole high-k stack with minimum trapping to the high-k stack. In addition, at the high temperature, the nc-CdSe embedded sample has the large relax current with the high discharge rate due to the increasing release of the trapped charges with large thermal energy. The charge retention capability of the device decreases with the increase of the temperature. For example, the device stressed at -6 V for 20 s will retain 30% of the original trapped holes at 20^oC, 23% at 70^oC, and 15% at 120^oC, respectively, after 10 years. This is because the stored charges gain the high thermal energy and the bulk high-k film is more conductive at the high temperature.