The single crystal diamond was treated in hydrogen plasma formed by microwave plasma chemical vapor deposition equipment, and the normally-off hydrogen terminal diamond field effect transistors with different gate lengths were prepared by atomic layer deposition of HfO₂ as gate oxide. We studied the effect of hydrogen treatment time and HfO₂ gate oxide on hydrogen terminal diamond field effect transistor. The experimental results showed that the HfO₂ gate oxide was suitable to fabricate hydrogen terminal diamond field effect transistor and exhibited a normally-off characteristic, which is advantageous for the fabrication of power devices. Furthermore, with increasing the gate length, the drive current density, threshold voltage and transconductance of the diamond device decreased.

In the drive for scaling of electronic devices one approach has been the integration of functionality into the back end of line (BEOL). Thin film transitors (TFT) are one such component with high quality devices being realised by PVD indium-gallium-zinc oxide (IGZO). However, the limitations of the PVD deposition process in terms of reliability and coverage in complex 3D topologies is of concern, where uniform sub nanometre films that demonstrate high mobility are required.

Here we have used atomic layer deposition (ALD) to deposit both nano-crystalline/amorphous ZnO and IGZO based laminate structures to generate high mobility thin film materials with sub-nm thickness control. Materials were grown using both thermal and plasma processes on a 200 mm Picosun R200 ALD system. Characterisation, in terms of morphology and composition, were achieved through electron microscopy, x-ray diffraction and x-ray photoelectron spectroscopy. Electrical properties were assessed via 4-point probe and both AC and DC Hall measurements.

Due to its unique flexibility, efficient and low-cost manufacturing process, and broad application prospects in the information and energy fields, flexible electronic technology has drawn more and more tremendous attentions. Among them, polymer-based high density metal/insulator/metal (MIM) capacitors have triggered a massive amount of research efforts in searching for the most applicable materials and fabrication processing.

In this work, we reported the fabrication and electrical properties of Hf-Ti-O and Hf-Sn-Ti-O MIM capacitors on polymer substrates (PET, PI and epoxy) by plasma-enhanced atomic layer deposition (PEALD). The effect of precursor and cycle ratio on electrical properties of MIM capacitors has been investigated. Organic tetradimethylaminohafnium (TDMAH), inorganic TiCl₄ and SnCl₄, or tetradimethylaminotitanium (TDMAT) and tetradimethylaminotin (TDMASn) were used as Hf, Ti, Sn metal sources, respectively, with plasma O₂ as O source. The deposition temperature was set to 80~100 ^oC. By tuning the pulse cycle ratio and cycle number of PEALD, the electrical properties of the Hf-Ti-O and Hf-Sn-Ti-O MIM capacitors were optimized. When the cycle ratio of HfO₂: TiO₂ was 2: 4, the sample of Hf_0.82Ti_0.23O₂ on polymer substrates with total 210 cycles showed larger capacitance density of 7.5 fF/μm² and leakage current density of 1.9×10^-4 A/cm² at -3 V. When the cycle ratio of HfO₂: SnO₂: TiO₂ was 6: 5: 4, Hf_0.81Sn_0.06Ti_0.18O₂ capacitor on polymer substrates with total 300 cycles exhibited better electrical properties of capacitance density of 8.0 fF/μm² and leakage current density of 1.9×10^-5 A/cm² at -3 V. When the bending radius was no less than 8.2 mm, polymer-based MIM capacitors displayed stable electrical properties without significant change. These results indicate that PEALD Hf-Sn-Ti-O dielectrics on polymers are promising candidate for flexible high-density MIM capacitors application.

MIM capacitor was developed herein with ALD-fabricated HfAlO_x dielectric layer. MIM capacitor is a key building element in modern CMOS platforms. It may occupy a significant part of the chip area. The high-k dielectric materials were introduced in the advanced production to minimize the footprint area of MIM: HfO₂-based materials grown by ALD replaced conventional dielectrics SiO₂ and Si₃N₄. To prevent the uncontrolled crystallization of amorphous HfO₂ film in a monoclinic phase that degrades its electrical parameters, some dopants (i.e. alumina) are introduced in deposited HfO₂ layer: the composite HfO₂/Al₂O₃ remains amorphous at deposition and during BEOL annealing processes.¹ Thus, amorphous materials are usually used in MIM capacitors located in BEOL. Hafnia doping enhances the composite crystallization (T≥600˚C) into metastable phases of higher symmetry having significantly higher k-value (30-40).² Crystalline HfAlOx dielectric has been employed in low voltage capacitors used in DRAM. Some CMOS applications (RF, CIS) require HV MIM capacitor (operating voltage 2.5-3.3V) located as DRAM in IMD0, to benefit from the attractive properties exhibited by crystalline HfAlOx. The increased operational voltage of HV MIM entails thicker dielectric layers compared to those used in DRAM. To take advantage of crystallinity of the HfAlOx film, engineering of the film growth and its crystallization parameters should be optimized for the required film thickness of the HV MIM capacitor. The developed capacitor with EOT≤2nm shows excellent dielectric integrity (V_BVD≥8V) along with the low leakage current.

Table 1 presents the plan of experiment where HfO₂-Al₂O₃ laminated stack (12:1) was deposited by ALD in the same run on two types of substrates: Si/SiO2/TiN(70nm) – structure A (MIM) and p-Si/thermal SiO₂(6.4nm) – structure B (MOS). The stack thickness is 14nm. Both pre-deposition (PreDA) and post-deposition (PDA) annealing were performed at the same conditions (T>600˚C). The RTA processing of structure A samples (MIM) was applied in three different flows to distinguish between the effects produced by RTA on the TiN bottom electrode and on the HfAlO_x dielectric layer. Fig.1 shows the scheme of MIM capacitor. The results of electrical characterization are presented in Fig.2 and Table 2. The difference in electrical parameters of MIM capacitors were compared with the detailed structural study of samples 1, 2 and 3 performed by XRD (Fig.3) and TEM/STEM (Fig.5) techniques. Surface characteristics of the TiN electrode was shown in Fig.4. PreDA process allows to prevent the void formation at the TiN/HfAlOx interface and to improve electrical integrity of sample 2.

High quality metal-oxide-semiconductor (MOS) gate stacks with stable threshold voltage are required for future GaN-based power transistors ^[1]. Here, we report a route to the realization of GaN MOS-capacitors (MOSCAPs) with an ALD AlN interlayer between GaN and Al₂O₃ using a FlexAL ALD system. AlN was grown using plasma enhanced ALD at 300⁰C using TMA and N₂ and H₂ plasma. The GaN samples were first exposed to an N₂ 150W 5min plasma pre-treatment followed by in-situ ALD of approximately 2nm of AlN. A 20nm Al₂O₃ was then deposited in-situ using thermal ALD at 200⁰C using TMA and H₂O. The results from these samples were then compared with MOSCAPs that had only an N₂ 150W 5min plasma pre-treatment followed by a 20nm thermal ALD Al₂O₃ layer.

20nm Pt/ 200nm Au contacts were deposited ex-situ as the gate contact and the MOSCAPs were measured at room temperature using capacitance-voltage (C-V) and current-voltage (I-V) measurements. The C-V measurements were used to calculate the hysteresis and frequency dispersion of these samples. The hysteresis included the flat band voltage difference between the forward and backward sweep of the C-V curve when swept from -5 to +5V and back to -5V at 1MHz. The frequency dispersion gives the maximum difference in the flat band voltage for C-V curves measured at various frequencies ranging from 1MHz to 1kHz (1MHz, 500kHz, 100kHz, 10kHz and 1kHz).A flat band voltage hysteresis and a frequency dispersion of 200mV was observed for samples that only had an Al₂O₃ gate dielectric while the insertion of an AlN interlayer resulted in a hysteresis and a dispersion of 50mV.

The I-V measurements produced a leakage of 0.016mA/cm² at 1V for the sample with only Al₂O₃ while the one with the interlayer produced a leakage of 0.0096 mA/cm² at 1V. These positive improvements with the insertion of an AlN interlayer could result due to the prevention of GaO_x sub-oxide formation at the GaN-Al₂O₃ interface ^[2].

In summary, the insertion of a PE-ALD AlN interlayer between an N₂ plasma treated GaN surface and ALD Al₂O₃ gate dielectric reduces the C-V hysteresis and frequency dispersion by 75% and decreases the leakage current by 40%. Both of these are encouraging for the realisation of high performance GaN power transistors.

1. Fiorenza, P., et al, “Slow and fast traps in metal-oxide-semiconductor capacitors fabricated on recessed AlGaN/GaN heterostructures” . Appl. Phys. Lett.106, 1–5 (2015).

2. Liu, S. et al., “Interface/border trap characterization of Al2O3/AlN/GaN metal-oxide-semiconductor structures with an AlN interfacial layer.”, Appl. Phys. Lett.106, 2–6 (2015).

As the size of the DRAM is scaled down, the new high-k dielectric materials have received considerable attention. Among high-k materials, the dielectrics based on Zr- and Hf- have extensively been used in semiconductor industry. However, there is a limitation to obtaining an equivalent oxide thickness of under 0.5nm. Therefore, to replace the high-k material based on Zr- or Hf-, new high-k materials, such as rutile-TiO₂ and perovskite oxide, have attracted a candidate in next generation DRAM devices. Meanwhile, 2-D perovskite oxide films made by Langmuir-Blodgett method were reported that the permittivity was measured over 200.[1] However, Langmuir-Blodgett method can’t be applied to electronic applications, especially on the substrate with a high aspect ratio.

Therefore, in this paper, Sr_xNb_yO_z (SNO) thin films with 2-D perovskite structure were deposited on TiN and SrRuO₃ substrate using atomic layer deposition (ALD). Then, rapid thermal annealing and laser annealing were performed for crystallization of thin films. Finally, we analyzed physical and electrical properties by RBS, TEM, XRD and semiconductor parameter analyzer.

Silicon carbide is one of most promising substrates for the power Metal Oxide Semiconductor Field Effect Transistor (MOSFET) and other power electronic devices. Due to high density of interface states (D_it) at SiO2/SiC interface, the mobility of Si-face (0001) 4H-SiC MOSFETs remains extremely low. Incorporations of nitrogen and phosphorous into the thermal oxide through a high temperature anneal are proven to be effective to suppress the D_it. Although the presence of nitrogen or phosphorous improves the mobility, achieved mobility values remain low when compared to the bulk SiC mobility. Additionally, nitrogen and phosphorous incorporations lead to negative threshold voltage (V_T) shift and makes even normally on devices. A positive enough threshold voltage is necessary for safe and reliable operation of power devices. Therefore, to deal with this trade-off between mobility and threshold voltage, deposited dielectrics on 4H-SiC have attracted more research interest to replace the thermal oxide. With deposited gate dielectrics, the substrate consumption is minimized and thus the carbon related defects associated with thermal oxidation can be avoided. Using deposited dielectrics also enables interface engineering to control interface properties independently. Among various deposition method, the atomic layer deposition (ALD) technique has proven to provide good film quality, low substrate damage, precise thickness control, and low temperature processing. This work first evaluates device electrical characteristics and reliability of SiO₂grown by either thermal or plasma ALD. SiO₂is the most suitable dielectric due to its large bandgap as well as a high conduction band offset to SiC resulting in suppression of electron tunneling current in SiC MOS devices. It was found that the channel mobility is similar between thermal and plasma ALD SiO₂but thermal ALD oxide shows lower threshold voltage compared to the plasma ALD oxide. Although ALD SiO₂provides positive threshold voltage and good gate insulating property, the SiC/SiO₂interface requires further treatment to enhance the mobility. We have recently demonstrated a novel interface engineering technique to improve the MOSFET mobility by combining ultrathin lanthanum oxide (LaO) at the SiC/dielectric interface and ALD SiO₂. In this study, we deposited ultrathin 1nm LaO followed by 30nm SiO₂using ALD tool without breaking the vacuum. It was found that the channel mobility is enhanced with the incorporation of 1nm LaO between SiC and SiO₂as compared to the device without LaO layer. This combination of ultrathin LaO and SiO₂provides an effective solution to challenges of SiC MOSFETs for power applications.

Memristor is a nonlinear and two-terminal passive device, which has ability to change the resistance between high resistive states and low resistive states by applying bias voltage. This property called resistive switching makes the memristors suitable for a wide range of applications in nonvolatile random access memory, dynamic random access memory and flash memory. In recent years, Metal-oxide based memory devices have drawn significant attention due to their high-density integration, high endurance, fast switching behavior, low power consumption and simple structure. In addition, among the promising binary transition metal oxide materials, such as nickel oxide, zirconium oxide, zinc oxide, hafnium oxide, and titanium oxide, TiO₂ films are extensively used to fabricate the nonvolatile memristor devices due to its simple structure and compatible with CMOS integration process. Recently, ZnO has been widely used for various applications due to its good electrical conductivity, wide band gape (3.37 eV), high exciton binding energy (~60 meV), low cost, nontoxicity, high mechanical and thermal stability. When doped with Aluminum ZnO grown via atomic layer deposition (ALD) has been reported to show resistivity values ranging from insulating to on the order of 10⁻³ Ω·cm, which is suitable for memory device electrodes.

Currently, the most common methods used were magnetron sputtering, pulsed laser deposition, thermal oxidation, electrodeposition, chemical vapor deposition, sol gel chemical reaction, and atomic layer deposition. The ALD is a self-limiting technique that allows atomic layer growth each time. ALD can precisely control the film layer thickness, stoichiometry, composition, uniformity, and sharp interface. ALD also shows perfect conformal coverage when it deposits thin film on complex surface structures. Therefore, ALD is considered as a novel and competitive method to deposit MIM memory structures. To create such devices, transparent Al:ZnO film was grown on Si wafers as an transparent electrode followed by an active layer of TiO₂ film, then the other layer of Al:ZnO was deposited in-situ on the TiO₂ layer to form memristor structures. All the thin films in the structures were synthesized by the ALD system sequentially.

Several physical characterization techniques have been employed to determine the ALD films of memory devices. The crystal structure was analyzed by X-ray diffraction. The film morphology was determined by field emission scanning electron microscopy. The surface roughness was analyzed by atomic force microscopy. The electric properties were measured by semiconductor analyzer. The results demonstrate a fairly good memristive device.

For thin film semiconductor device applications, the formation of high quality contacts is critical. Currently, it is difficult to realize ohmic contacts on zinc oxide (ZnO) thin films especially for applications that require more resistive active layers e.g. thin film transistors (TFTs) and Schottky diodes. In this work, we investigate the contact resistance in thin film devices that employ ZnO active layers grown by low temperature plasma-enhanced atomic layer deposition (ALD) with the gated transmission length method (TLM). The contact performance in intrinsic ZnO devices are compared to identical devices but with a homogeneously doped ALD zinc tin oxide (ZTO) interlayer inserted between the semiconductor body and metal contact. By incorporating a small percentage of tin (Sn) in the ZnO during ALD growth, we observed an increase in the film’s electron concentration resulting in lowered contact resistance.

Al_xGa_1-xN and GaN films were obtained using Plasma enhanced Atomic Layer Deposition (PE-ALD) at 300 °C, we study the effect of Al content variation on the optical and structural and electrical performance. XRD measurements show the hexagonal structure, SIMS profile signals reveals the main components of Al_xGa_1-xN.

Experimental

AlGaN thin films were deposited on silicon wafers via atomic layer deposition using a mega cycle which consists of sub cycles of AlN and GaN to obtain the Al_xGa_1-xN alloy. The AlN sub cycle consist of (1) pulse of Trimethyl Alluminium (TMA), (2) Ar purge, (3) H₂/N₂ plasma and (4) Ar purge, the growth ratio is (0.5Å/cycle) at 300°C, the total number of megacycles were 215. GaN sub cycles consist of (1) pulse of Trimethyl Galliu (TMGa), (2) Ar purge, (3) H₂/N₂ plasma and (4) Ar purge, the growth ratio is (0.2Å/cycle) at 300 °C, the total number of megacycles were 131. The number of megacycles were calculated in order to obtain ~20 nm.

Results

The XRD patterns of Al_xGa_1-xN on silicon substrates growth with 0.3 and 0.6 Al content were performed. Two peaks were observed in the sample Al_0.3Ga_0.7N the peak located at 2θ=34.5° (002) is assigned to hexagonal phase of GaN and a second peak at 2θ=32.3° (100) correspond to the hexagonal phase of AlN. The sample Al_0.6Ga_0.4N show peaks at 2θ=32.3° , 34.3° ,37.0° assigned (100), (002), (100) AlN. Furthermore, from photoluminescence characterizations it is possible to observe in the Al_0.3Ga_0.7N sample a yellow luminescence band situated at 2.32 eV, which is related to Gallium and N vacancies, carbon defects, as well as to the high concentrations carriers 10¹⁹ cm^-3 [1]. The peak observed at 2.2 eV is associated to dislocations defects [2]. However, a sample which contains higher content of Al didn’t show PL signal.

On the other hand, by SIMS sputtering time profile it is possible to observed that the sample with Al_0.3Ga_0.7N show a non-uniform Al content, although Al_0.6Ga_0.4N show a better Al distribution film. Electrical characterizations of the deposited films will be also included.

High-k metal gate (HKMG) technology has been introduced since the 45-nm node complementary metal oxide semiconductor (CMOS). The gate-first process was replaced by the gate-last process because of the threshold voltage pinning caused by the subsequent high-temperature process¹. The gate-first process provides a capability to reduce the process complexity, and is more economic than the gate-last process. To realize high-performance MOS field-effect transistors (MOSFETs) using self-aligned gate-first process, the thermal stability of MOS structure must be excellent to sustain the subsequent high temperature process. With the higher electron mobility, GaAs-based III-V semiconductors have potential to replace the current Si-based CMOS technologies. However, the reported thermal stability between high-k/III-V was limited to 500~600^oC caused by the inter-diffusion. In our previous study, ultra-high thermal stability above 850^oC between in-situ grown oxide/III-V interface was attained^2,3, critical for the present study of atomic layer deposition (ALD)-TiN/oxide/(In)GaAs thermal stability at temperatures ranging from 850 to 950°C. Here, we have studied the samples with different post-metallization annealing (PMA) using transmission electron microscopy (TEM), J-E, and C-V characteristics of the MOS capacitors (MOSCAPs). The samples were prepared in a ultra-high vacuum (UHV) multi-chamber growth/analysis system ( Fig. 1 ). The detailed fabrication process and the schematic structure of the MOSCAPs are shown in Fig. 2 . The TEM shows the smoothness in an atomic scale of the ALD-TiN/high-k/(In)GaAs interfaces. The interface remained intact without degradation after 800^oC 5s in He ambient ( Fig. 3 ). From the J-E curves (Fig. 4), the leakage current densities of the MOSCAP with different PMA in N₂ show no degradation after 900^oC annealing for 10s. The leakage current density of the MOSCAPs maintained below 10^-7 A/cm² at electric fields of ± 4 MV/cm, which is the same with that of the MOSCAP without PMA. A different behavior was found in the MOSCAP with PMA in He. The leakage current density raised sharply in the negative bias region, probably resulted from the generation of nitrogen vacancies during the high temperature annealing in He. Similar features were found in the C-V characteristics ( Fig. 5 ). With the PMA in N₂, the C-Vs showed no degradation after 900-950^oC annealing, while the MOSCAP was too leaky to measure the C-Vs for the MOSCAP with PMA in He with temperatures above 900^oC. The excellent electrical and thermal stability of the MOS structures with TiN gate are vital to realize high performance GaAs inversion channel MOSFETs using a gate-first process.

Germanium (Ge) has attracted tremendous interest as a channel material for high performance complementary metal-oxide-semiconductor (CMOS) devices. The interfacial cfixed charges are detrimental to the performance promotion of Ge MOSFET devices as they can form Coulomb scattering center to reduce channel carrier mobility and device reliability. Thus we experimentally investigate the interfacial defect in the GeO_x/Al₂O₃ gate stack grwon by ALD using X-ray photoelectron spectroscope (XPS) and electrical charateristics by capacitance-voltage (C-V) measurement. For GeO_x interlayer by ozone oxidation, oxygen vacancies exist and show positive charges at the Ge/GeO interface. The O₂ annealing is helpful to decrease the oxygen vacancy defect. For the GeO_x/Al₂O₃ interface, oxygen dangling bonds exist, and show negative charges. This work can be effectively applied to engineer the interface promotion and enhance the performance of Ge-based devices.

Refractory metal nitrides and carbides, deposited by ALD, are attractive for gate metallization of 3D metal-oxide-semiconductor (MOS) devices, due to the good thermal and chemical stability and metal effective work function (EWF) variation capability. However, obtaining low resistivity of the gate metallization is challenging. Therefore, a bilayer approach, where a thin refractory metal carbide/nitride liner capped by a pure metal, is implemented. The liner determines the EWF and serves as a nucleation layer and a diffusion barrier for the contact metal. Currently, Tungsten is commonly used as a local interconnect conductor. Due to its resistivity and device performance challenges, Molybdenum is considered as an alternative capping layer.

The objective of the current research is to investigate the structural and the electrical properties of a bilayer metallization: thermal-ALD tungsten carbo-nitride, WCN (WC_xN_y), liner with thicknesses of 10/20/30Å covered by 100Å CVD-Mo cap. The evolution of the properties upon annealing at 750^oC in forming gas (FG -10%H_2, 90%Ar) and vacuum (10^-6torr) is correlated with the values of the EWF on thermal SiO₂ and on ALD Al₂O₃/SiO₂. The metal stack structure and composition were studied by XRD, STEM-EDS, and ToF-SIMS. The sheet resistance was measured by the four-point probe technique. The EWF of the WCN/1kÅ Mo metal stack on SiO₂ and on Al₂O₃ was studied using capacitance-voltage measurements of MOS devices by plotting the flat-band voltage versus the effective oxide thickness.

It was found that the lowest sheet resistance of as-deposited samples was obtained for the metal stack on the 10Å WCN liner (26Ω/□); annealing at FG led to sheet resistance decrease up to 11Ω/□. The EWF of the as-deposited samples is determined by the WCN layer: a value of 4.8eV on SiO₂, as was obtained by a 30Å WCN/W reference sample, and a value of 5.35eV on Al₂O₃/SiO_2, demonstrating a difference of ~0.4eV attributed to a dipole at the Al₂O₃ /SiO₂ interface, earlier obtained in our group. Both thermal treatments induced Mo diffusion towards the interface with the dielectric, but the annealing ambient effect on metal crystallinity and Mo diffusion rate is different. Annealing at vacuum caused grain growth of the cubic W₂N phase and stabilization of the EWF to a value of 4.8eV on SiO₂. FG annealing led to BCC-Mo grain growth, significant Mo diffusion towards the interface, and EWF on SiO₂ decrease of 0.2eV. Similar EWF decrease due to FG annealing was observed on Al₂O₃. This, combined with the low resistivity, makes WCN/Mo stack a good candidate for many applications, e.g. FDSOI devices.

We have investigated the properties of ultrathin Al₂O₃and MgO in metal-insulator-metal (M-I-M) trilayers fabricated using in situ integrated sputtering and atomic layer deposition (ALD). The quality of ultrathin Al₂O₃ was found to be significantly dependent on the pre-ALD conditions which lead to extremely different M-I interface. After optimization of ALD processing parameters, M-I interfacial layer (IL) was reduced to a negligible level obtaining a dielectric constant (ε_r) up to 8.9 on the Al₂O₃films in a thickness range between 3.3-4.4 nm, corresponding to an effective oxide thickness (EOT)~1.4-1.9 nm respectively comparable to high-K dielectrics. While ε_r decreases at a smaller Al₂O₃ thickness, the hard-type dielectric breakdown 32 MV/cm and in situ scanning tunneling spectroscopy (STS) revealed band gap ~2.63 eV confirming high quality dielectric as good as an epitaxial Al₂O₃ film. This result suggests that the IL is unlikely a dominant reason for the reduced ε_r at the Al₂O₃ thickness of 1.1-2.2 nm and is due to electron tunneling as supported by transport current-voltage measurement. However, non-optimal conditions result in the growth of significant IL with drastically reduced ε_r~0.5-3.3. The properties of MgO with and without 5C-ALD Al₂O₃ studied in the thickness range 2.5-5 nm point out significance of seed layer in fabrication of high-quality dielectrics, approaching ε_r~9 for 5C-ALD-Al₂O₃/ALD-MgO at thickness 3.8-4.9 nm corresponding to EOT~1.6-2.1 nm respectively. But, 40C-ALD MgO without seed layer has unexpectedly lower ε_r~3-4 possibly due to poor nucleation forming an interfacial layer, and correspondingly increase in the leakage current. The similar decreasing trend in ε_r with decrease in MgO thickness is observed but at thickness greater than that of Al₂O_3, due to higher leakage current observed for MgO dielectrics and also confirmed by in situ STS analysis. Our results demonstrate the significance of controlling the nucleation in ALD to achieve better M-I interface in order to fulfill the demand for leak-free and defect-free high-quality ultrathin dielectrics an alternative for low-cost gate dielectric for CMOS, and tunnel junction for quantum computing and memory applications.

Atomic layer deposition (ALD) of metallic ternary TiSiN films is associated with a variety of morphological and structural variations. Among these phenomena are the thickness and stoichiometric-dependent amorphous to crystalline phase transitions, film density changes, surface roughness and film resistivity variations. In the case of TiSiN films deposited via thermal ALD at temperatures of about T<600° C, using chlorine-based Si precursors, titanium tetrachloride and ammonia, the film structure is highly dependent on the total Si incorporated in the film. In this work, we demonstrate the tunability of crystalline phase in highly conformal TiSiN films with varied Si content. TiSiN films were deposited on high aspect ratio structures using a Eugenus 300mm commercial QXP mini-batch system. Film thickness and Si content were varied, and corresponding structural analysis was performed using multiple characterization techniques. X-ray diffraction and reflectivity studies of these films showed a reduction in film density and transition from nano-crystalline to pure amorphous phase with increase in Si fraction. Cross-section high resolution transmission electron microscopy (HRTEM) and selected area electron diffraction (SAED) pattern analyses corroborates with the X-ray analysis that high-Si TiSiN films exhibit a fully amorphous structure. Moreover, control of Si fraction in the film enables tuning of the morphology from polycrystalline to fully amorphous; in all cases, excellent step coverage on high aspect ratio structures were obtained.

The advancement of fabrication techniques for nanostructures devices has led to technological breakthrough in semiconductor industries. Apart from the lithographic developments, high-κ materials like ZrO₂ and HfO₂ have been employed as gate dielectric for efficient control of the carrier density. In this regard, atomic layer deposition (ALD) has been used to grow these insulators as it produces highly uniform and conformal layer with precise thickness. Previous works to grow HfO₂ by ALD require higher temperature (>100 ^oC ) for microelectronic devices has been done. However, many devices and materials have additional constraints that their properties degrade at higher temperatures. This limits the operating temperature at which the various fabrication processes can be carried out. For our research in the field of topological physics, mercury telluride (HgTe) topological insulators (Tis) are significant due to its versatility and tunability from trivial to 2D TI to 3D TI to Weyl by tuning the thickness and applied strain (compressive or tensile). However, the transport properties degrade when the HgTe wafer are heated above 80 ^oC . To overcome this problem, we have developed a room temperature ALD process for growing HfO₂. A comprehensive study of structural and transport properties of devices containing HfO₂ gate dielectrics was carried out and results has been compared to device containing coventional SiO₂/ Si₃N₄ multilayers insulator films grown by plasma enhanced chemical vapour deposition (PECVD).This comparison demonstrates that our ALD grown insulator is superior in terms of structural properties. We have already shown that microstructures fabricated with ALD grown insulator shows quantum spin hall effect for 2D HgTe based devices. This capability is critical for understanding the properties of microscopic devices and may provide new insights in the field topological insulators. Our process is not just limited to HgTe (e.g. we use Si for process control) but can be easily adapted to other material systems which also require low temperature lithography process in order to retain the intrinsic property of material.

β-Ga₂O₃ power device with metal-oxide-semiconductor (MOS) structure have been widely investigated. Al₂O₃ is the leading candidate as gate insulator because of relatively stable amorphous structure, a high dielectric constant (k) of 8 - 9 and a large bandgap of 6.5 - 6.8 eV. Al₂O₃ films are generally formed by atomic layer deposition (ALD). However, it remains big issues such as an abnormal flatband voltage (V_fb) shift and a large interface state density (D_it). To improve these electrical properties, various surface cleaning techniques of the substrate have been considered. In this study, we investigate how the surface cleaning technique affects to morphology of the surface of β-Ga₂O₃ and electrical properties of Pt/Al₂O₃/β-Ga₂O₃ MOS capacitors.

At first, n-β-Ga₂O₃ epilayer (2.0 × 10¹⁶ cm^-3) / n⁺-β-Ga₂O₃ (3.7 × 10¹⁸ cm^-3) substrates (n-β-Ga₂O₃) were cleaned under four conditions: just a SPM for 5min, and SPM for 5 min (SPM), followed by BHF for 1 (BHF1), 10 (BHF10), and 30 min (BHF30). 25-nm-thick Al₂O₃ films were deposited on n-β-Ga₂O₃ substrates by ALD at 300 °C using TMA precursor and H₂O gas. Finally, Pt gate electrodes and Ti/Pt ohmic electrode were deposited.

The minimum root mean square (RMS) value (0.36 nm) of the n-β-Ga₂O₃ substrate was observed after SPM treatment. The RMS values (~ 0.6 nm) increased drastically when BHF treatment carried out even for 1 min and the value was unchanged even if treatment time was longer. In addition, the n-β-Ga₂O₃ substrate was etched by 0.9 nm for the BHF30. This is because the increase of the surface roughness is due to the heterogeneous etching of the n-β-Ga₂O₃ substrate. The Al_2p XPS intensities of the Al₂O₃ films after ALD 5 cycles for the BHF10 and BHF30 decreased by about 25 % compared to the SPM and BHF1, suggesting that the surface roughness affects to the initial growth of the Al₂O₃.

The MOS capacitor exhibited similar J-V properties regardless of the surface treatment techniques, indicating that the characteristic of the Al₂O₃ films was unchanged. On the other hand, the V_fb hysteresis (V_{fb hys}) due to the trapped/detrapped electrons increased as the BHF treatment time increases. The D_it energy distribution due to the fixed charge, which was calculated using conductance method, increased with increasing the BHF treatment time. These V_{fb hys} and D_it behaviors are in good agreement with the data of the surface roughness of the n-β-Ga₂O₃ substrate. Considering to these data, note that the fixed charge and trapped/detrapped electrons occur at the Al₂O₃/n-type β-Ga₂O₃ interface. Therefore, the BHF surface treatment technique is not necessary promising from the viewpoint of the interface characteristics.

We developed an advanced plasma-assisted atomic-layer-deposited (PA-ALD) HfO_xN_y process targeted on InGaAs substrate. The developed ALD process is consisted of isopropyl oxidant precursor and in-situ cyclic N2 plasma nitridation that improves both interface and dielectric bulk quality as well. The interface chemistry and capacitance-voltage characteristics of HfO_xN_y / InGaAs MOS devices are investigated. Clear oxide related elements were eliminated using our ALD process confirmed by XPS and STEM measurements. The IPA-based HfO_xN_y/n-In_0.53Ga_0.47As MOS capacitor exhibited a significant decrease of interface trap density, D_it, of 4.5×10¹¹ eV^-1cm^-2 at E_c - E_t = 0.3 eV and outstanding inversion behaviors. Morevover, substantial improvement was found not only in n-type substrates but also in p-type substrates as well. The significant mid-gap D_it decrease is responsiblefor this inversion behavior. The improvement mechanism of the proposed technology is assumed to be that nitrogen incorporation reduces oxygen vacancies which act as oxygen diffusion paths and with the use of IPA oxidant the interface would be strongly protected during pre- and post-dielectric deposition. Detailed electrical characteristics such as positive-bias-temperature-instabiltiy characteristics were investigated.