High-k Dielectrics for III-V Electronics (EM+SS-WeA)
Wednesday, Oct 20 2010 2:00PM, Room Dona Ana
Moderated by: Andrew C. Kummel, University of California at San Diego
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2:00 PMEM+SS-WeA-1High-k III-V MOSFETs Enabled by Atomic Layer Deposition
2:40 PMEM+SS-WeA-3Passivation of Al2O3/InGaAs(100) Interfaces by Atomic Layer Deposition and Annealing
3:00 PMEM+SS-WeA-4An In Situ Examination of Atomic Layer Deposited Al2O3/InAs(100) Interfaces
4:00 PMEM+SS-WeA-7Fermi-level Unpinning of HfO2/In0.53Ga0.47As Gate Stacks using Hydrogen Anneals
4:20 PMEM+SS-WeA-8Valence Band Alignment in low-k Dielectric/Cu Interconnects as Determined by X-ray Photoelectron Spectroscopy
4:40 PMEM+SS-WeA-9III-V CMOS: A sub-10 nm Electronics Technology?
5:20 PMEM+SS-WeA-11Potential Profiles of III-V MOSCAPs with Kelvin Probe Force Microscopy In Situ
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