ALD/ALE 2024 Session ALE-MoA: ALD+ALE and Emerging Topics in ALE

Previously we have reported on the development of thermal atomic layer etching methods to remove the native oxide of aluminum prior to encapsulation with ALD fluoride dielectric materials. The ALE process is based on cyclic exposure to trimethylaluminum and anhydrous hydrogen fluoride. Co-reaction with alkali halide materials like LiF and KBr can enhance the effective aluminum oxide etch rate and/or reduce the substrate temperature threshold where continuous etching dominates the cyclic reaction over deposition. In this new work, we report on the use of CsF as an enhancing agent and show that aluminum oxide ALE can be achieved at substrate temperatures as low as 125 °C during exposure to TMA and HF. The benefit of this temperature reduction includes minimizing the amount of etch damage experienced by the underlying Al layer.

The use of this ALE process followed by ALD MgF₂ is shown to yield protected Al mirror coatings with greater than 85% reflectance at 120 nm, comparable to best results achievable by conventional PVD methods. We will discuss chamber modifications to enable this low temperature ALE process and possible future applications related to the NASA flagship astrophysics mission Habitable Worlds Observatory. We also describe how the combination ALE/ALD approach can benefit other Al structures including ultraviolet bandpass filters and superconducting detectors. The ALE temperature reduction is also shown to be capable of continuous Al etching which yields an isotropic gas phase etching process for thin Al films.

Atomic layer deposition (ALD) and atomic layer etching (ALE) techniques were used to deposit and etchback a thin ZrO₂ shell on TiO₂/ZrO₂ core/shell nanoparticles. Possible pinholes in the initial ZrO₂ shell on the TiO₂/ZrO₂ core/shell nanoparticles were minimized by first growing thicker ZrO₂ films by ZrO₂ ALD. These thicker ZrO₂ ALD films were then etched back to produce thinner more continuous ZrO₂ films. The ALD and ALE were performed while the nanoparticles were agitated using a rotary reactor. ZrO₂ ALD films were deposited using sequential, self-limiting exposures of tetrakis(dimethylamino) zirconium (TDMAZ) and H₂O. Self-limiting conditions for the ZrO₂ ALD were determined by monitoring the pressure during multiple micropulses of the ALD reactants. Ex situ analysis of the nanoparticles was performed using transmission electron microscopy (TEM) to observe the growth of the ZrO₂ shell on the core/shell TiO₂/ZrO₂ nanoparticles. The ZrO₂ ALD led to more spherical ZrO₂ shells on the crystalline and more irregular TiO₂ cores in the absence of nanoparticle aggregation. The ZrO₂ ALD on the nanoparticles had a growth rate of 1.1 Å/cycle. Tunable ZrO₂ coatings were observed with thicknesses ranging from 5 nm to 25 nm after up to 250 ZrO₂ ALD cycles. The ZrO₂ deposited film was then etched back using sequential HF and TiCl₄ exposures. Self-limiting conditions for the ZrO₂ ALE were again determined by monitoring the pressure during multiple micropulses of the ALE reactants. Quadrupole mass spectrometry (QMS) experiments also identified ZrCl₄ etch products and TiF_xCl_y ligand-exchange products during the TiCl₄ exposures. Ex situ TEM studies revealed that the spherical ZrO₂ shells were maintained during the ZrO₂ ALE with no observable nanoparticle aggregation. The ZrO₂ ALE on the nanoparticles had an etch rate of 6.5 Å/cycle. Tunable ZrO₂ coatings were produced by the ZrO₂ ALE from 25 nm back down to 5 nm using 30 ZrO₂ ALE cycles. This procedure employing ZrO₂ ALD and ZrO₂ ALE provides exceptional control over the ZrO₂ shell thickness and quality on the TiO₂/ZrO₂ core/shell nanoparticles.

The mitigation of substrate damage is crucial to any process at the atomic scale (1). This is especially true for device technology applications in which source/drain and metalized regions are susceptible to damage (2). To eliminate substrate damage, we have developed plasma-enhanced atomic layer deposition (PEALD) of silicon nitride without ion bombardment (3).

The removal of native oxide on the Si wafer before depositing Si₃N₄ is also important for device performance (4). Removing the native oxides from the Si wafer using other means, such as reactive ion etching or wet etching, results in substrate damage and defects to the wafer.

Here, we will discuss the means of removing the native oxide from the Si wafer surface using Plasma Assisted Atomic Layer Etching (PAALE) prior to depositing silicon nitride. The PAALE process occurs in the same PEALD chamber, which prevents re-oxidation between steps. Furthermore, studies will be presented on the prevention of ion flux damage on the substrate surface with controlled ion energies and the possibility of performing PAALE without the incidence of any ions. The objective of the study is to develop a tool that can perform angstrom-precise PEALD and PAALE processes in the same chamber and prevent substrate damage.

References:

1. C. Cismaru, J. L. Shohet and J. P. McVittie, Applied Physics Letters 76 (16), 2191-2193 (2000)
2. C. Petit-Etienne, M. Darnon, L. Vallier, E. Pargon, G. Cunge, F. Boulard, O. Joubert, S. Banna and T. Lill, J. Vac. Sci. Technol. B 28 (5), 926-934 (2010)
3. US Patent # 9,972,501 B1 May 15, 2018
4. Dominik Metzler, Chen Li, C.Steven, “Investigation of Thin Oxide Layer Removal from Si Substrates Using an SiO2 Atomic Layer Etching Approach: The Importance of the Reactivity of the Substrate”

High-volume manufacturing of microelectronics relies on thousands of sequential patterning, deposition, etch, and surface smoothing steps to create integrated circuits comprised of interwoven metallic, semiconducting, and dielectric features. Throughout the fabrication process, surface roughness is carefully monitored to ensure proper adhesion between layers and maximize distance between features. If surface roughness exceed tolerance limits, films are more likely to delaminate and manufactured features are more like to short-circuit.¹ At sub-nm feature sizes these tolerances become more challenging to reach.

Current smoothing techniques either rely upon top-down mechanical polishing² or on plasma methods.³ Both techniques preferentially etch surface features, leaving a process gap for targeted surface smoothing on complex architectures. In pursuit of a more accessible smoothing methods compatible with complex architectures, we have identified a vapor phase method for smoothing gold surfaces using a known area selective small molecule inhibitor.⁴ We explore the kinetics of adsorption and desorption of a N-heterocyclic carbene (NHC) through in-situ quartz crystal microbalance (QCM) analysis and molecular dynamics (MD) simulations. QCM traces (Fig. 1) show a saturative growth behavior for the initial dose of NHC achieving a surfactant density of 97 ng cm^-2, while subsequent doses saturate to 60 ng cm^-2. These differences are attributed to a reduction in the total number of available surface sites through atomic smoothing.

To confirm this, changes in surface roughness were analyzed through atomic force microscopy (AFM). AFM images (Fig.2) show a significant reduction in calculated root-mean-square (RMS) roughness values between surfaces left untreated (2.97 nm), heated under vacuum (2.38 nm) and those treated with NHC heated under vacuum (1.87 nm).

Atomic layer etching (ALE) has found its place in advancing technologies as chip sizes continue to shrink and pitch sizes get smaller. The ALE process offers several advantages over conventional reactive ion etching (RIE) such as better directionality, uniformity, selectivity and damage free surface after etching [1,2]. A self-limited removal of material with minimal damage to the surface requires a good control over every step of the ALE process [3]. Quasi atomic layer etching (QALE) is defined as a process when more than one mono-layer of the material is etched per cycle. Surface treatment, Control of ion energies and appropriate evacuation of the chemical component (Cl₂) is necessary to control the etch rate per cycle and achieve etch saturation in a cycle sweep.

In our work, we have conducted in-depth studies to set up a molecular QALE process as seen in Figure 1 at our 300 mm facility in an inductively coupled plasma (ICP); decoupled plasma source (DPS) AMAT chamber on 350 nm amorphous Silicon (aSi) which was deposited on 12” blanket wafers. First, experiments were conducted to establish the bias power and pressure window. After this step, Ar sputter threshold for amorphous Silicon was determined. This was used as baseline to setup a cyclic process where the EPC was determined over low ion energies by optimising the bias power and activation time during exposure to Ar plasma. Damage or roughness caused to the layer being etched severely degrades device performance with decreasing dimensions [4]. Hence, to investigate the same, an Ellipsometer model was developed to understand the composition and thickness of this rough layer of the aSi surface post QALE etch. Thickness of the rough layer was evaluated over increasing number of cycles. The EPC for different Ar activation times at bias power 25 W is shown in Figure 2. The thickness of the rough layer at the end of the cycles is seen in Figure 3. We observed that the Ar activation time and no. of cycles have an influence on the thickness of the rough layer after etching.

In this work we investigate the factors and challenges that need to be taken into consideration while transferring the ALE process from lab to fab.In general, our work highlights the importance of control of every step in QALE for effective transfer and commercial viability in a 300mm line.